It is known that a receiver can be locked by input data a through a locking device with a phase-locked loop (PLL) circuit including a voltage controlled oscillator. The oscillator signal is employed to clock the writing of input data to a locking device and to track the input data at further transmission of the received signals to the other apparatuses. The locked condition is achieved at definite limitations on the initial matching error in phase and frequency of the voltage controlled oscillator (VCO) and input data (see F. M. Gardner. Phaselock Technique. J. Wiley & Sons, 1979, ch.4). If initial frequency or/and phase values exceed permissible limits, the PLL circuit will not achieve the locked condition. To expand the range of the initial frequency and phase values at which the PLL circuit can be locked by input data, a forced variation of frequency and/or phase is employed.
In digital communication system receivers, the PLL circuit can be phase locked to the VCO through the use, within the PLL circuit, of a phase detector and a supplementary unit for forced scanning of the controlled oscillator frequency (see F. M. Gardner. Phaselock Technique. J. Wiley & Sons, 1979, ch.5) or an input signal phase (T. N. Lee, J. F. Bulzacchelly. 155 MHz Clock Recovery Delay-and-Phase-Locked Loop. IEEE Journal of Solid State Circuits, v.27, No.12, pp 1736-1745). With the prior art device, a locking band of the PLL circuit is expanded owing to a coarse frequency or phase lock during scanning.
Described in F. M. Gadner. Phaselock Technique. J. Wiley & Sons, 1979, ch.5, is a digital receiver locking device comprising a phase detector and a decision unit, each one having inputs to which an information signal is provided, a VCO for generating a clock frequency for the phase detector and the decision unit, a low-pass filter (LPF) having an input coupled to an output of the phase detector, an analog adder having one input coupled to an output of the LPF, another input coupled to a saw-tooth generator via a controllable switch, and an output coupled to a control input of the VCO, and a block information signal decoder having an input coupled to an output of the decision unit, and an output coupled to a control input of the switch. The saw-tooth generator, the switch and the analog adder make up a frequency scanning unit.
In the above apparatus, a digital data signal is generated at the output of the decision unit, and a clock frequency locked to the digital signal is generated at the output of the VCO. If a block lock condition is systematically lost, the decoder generates a scanning enable signal, responsive to which the switch connects an output of the saw-tooth generator to an input of the adder. As the result, a saw-tooth voltage is generated at the adder output, causing a variation in the VCO generation frequency. Scanning of the VCO generation frequency is terminated when the decoder generates a control signal of appropriate level, that is provided to the switch.
A problem with the prior art locking device is a considerable time spent for initial locking. The reason is that a short-term loss of the PLL lock condition may result in scanning a control signal in a direction opposite to the optimum one.
Closely approaching the claimed invention from the viewpoint of technical essence is a locking device comprising a digital phase detector having a delay unit at an input and an analog adder at an output, a LPF and a VCO based on a quartz-crystal generator. An input data signal is provided to a first input of the delay unit, the delayed data from an output of the delay unit are, in turn, provided to first inputs of the phase detector and decision unit. From the LPF output, a signal is provided to a second control input of the delay unit. A signal of the VCO is provided to second inputs of the phase detector and decision unit. The phase detector has several outputs of a first and second type. Averaged weighted amplitude values of pulses generated at the inputs of the first and second type are used as the estimates of the VCO frequency lag and lead, respectively, relative to the input data frequency. To obtain the estimates, the analog adder combines appropriately weighted voltages generated at the first type outputs of the phase detector, and subtracts appropriately weighted voltages generated at the second type outputs of the phase detector. An output signal of the analog adder is averaged by the LPF, the averaged signal being provided to control inputs of the VCO and delay unit. To lock the VCO by input data, the oscillator frequency should be equal to a code generation frequency. A digital signal is provided from an output of the decision unit, and a clock frequency locked to the received digital signal is generated at the VCO output (see the aforementioned reference of T. H. Lee, J. F. Bulzacchelly).
The prior art locking device, however, exhibits a narrow locking band of the PLL circuit, resulting in a necessity to use a VCO based on a quartz-crystal resonator.